1 From c7ce6453b769c45006ed4983762f81e130878171 Mon Sep 17 00:00:00 2001
2 From: Shawn Lin <shawn.lin@rock-chips.com>
3 Date: Wed, 26 Nov 2025 07:26:39 +0800
4 Subject: [PATCH] mmc: sdhci-of-dwcmshc: Disable internal clock auto gate for
7 Enabling CMDQ support can lead to random occurrences of the error log when
8 there are RPMB access and data flush executed:
10 "mmc2: Timeout waiting for hardware interrupt."
12 Enabling CMDQ and then issuing a DCMD as the final command before disabling
13 it causes the eMMC controller to auto-gate its internal clock. Chip simulation
14 shows this results in a state machine mismatch after CMDQ mode exit, triggering
15 data-timeout errors for all subsequent read and write operations.
17 Therefore, the auto-clock-gate function must be disabled whenever CMDQ is
20 Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
21 Acked-by: Adrian Hunter <adrian.hunter@intel.com>
22 Fixes: fda1e0af7c28 ("mmc: sdhci-of-dwcmshc: Add command queue support for rockchip SOCs")
23 Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
25 drivers/mmc/host/sdhci-of-dwcmshc.c | 3 ++-
26 1 file changed, 2 insertions(+), 1 deletion(-)
28 --- a/drivers/mmc/host/sdhci-of-dwcmshc.c
29 +++ b/drivers/mmc/host/sdhci-of-dwcmshc.c
30 @@ -696,10 +696,11 @@ static void dwcmshc_rk3568_set_clock(str
32 sdhci_set_clock(host, clock);
34 - /* Disable cmd conflict check */
35 + /* Disable cmd conflict check and internal clock gate */
36 reg = dwc_priv->vendor_specific_area1 + DWCMSHC_HOST_CTRL3;
37 extra = sdhci_readl(host, reg);
40 sdhci_writel(host, extra, reg);
42 if (clock <= 52000000) {